1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having an internal circuit that performs a prescribed operation based on a constant current generated by a constant-current source circuit.
2. Description of the Background Art
Conventionally, in a semiconductor integrated circuit device such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), or the like, a constant-current source circuit is provided that is less likely to be affected by variations of an external power-supply potential extVdd or by process variations (variations of a threshold voltage of an MOS transistor). The constant current generated by the constant-current source circuit is transmitted to various internal circuits via a current mirror circuit. Each internal circuit performs a prescribed operation based on the transmitted constant current. Thus, a semiconductor integrated circuit device that is less likely to be affected by variations of an external power-supply potential extVdd or by process variations is realized.
FIG. 14 is a block diagram representing the main portion of a conventional semiconductor integrated circuit device. In FIG. 14, the semiconductor integrated circuit device is provided with a constant-current source circuit 81 and a plurality (four in the figure) of internal circuits 82 to 85.
Constant-current source circuit 81 includes resistance element 91 and 92, a capacitor 93, P-channel MOS transistors 94 and 95, and N-channel MOS transistors 96 and 97, as shown in FIG. 15. Resistance element 91 and capacitor 93 are connected in series between an external power-supply potential extVdd line and a ground potential GND line, forming a low pass filter. MOS transistors 94 and 96, resistance element 92, and MOS transistors 95 and 97 are respectively connected in series between a node N91 between resistance element 91 and capacitor 93 and a ground potential GND line. Gates of P-channel MOS transistors 94 and 95 are both connected to the drain of P-channel MOS transistor 94. Gates of N-channel MOS transistors 96 and 97 are both connected to the drain of N-channel MOS transistor 97. N-channel MOS transistors 96 and 97 together form a current mirror circuit.
The high frequency noise on an external power-supply potential extVdd line is removed by the low pass filter formed by resistance element 91 and capacitor 93 so that external power-supply potential extVdd devoid of the high frequency noise is provided to node N91. P-channel MOS transistors 94 and 95 are both set to operate in a sub-threshold region, and the current mirror circuit formed by N-channel MOS transistors 96 and 97 allows currents Ic of the same value to flow through P-channel MOS transistors 94 and 95.
A gate width W2 of P-channel MOS transistor 95 is set to be greater than a gate width W1 of P-channel MOS transistor 94 so that a voltage difference dV is created between P-channel MOS transistors 94 and 95 in gate-source voltages Vgs required to allow currents Ic of the same value to flow through P-channel MOS transistors 94 and 95. This voltage dV is ideally dV=kxc3x97T/qxc3x971n(W2/W1). Here, k indicates the Boltzmann""s constant, T indicates the absolute temperature, and q indicates the amount of charge of electrons. Therefore, dV is proportional to absolute temperature T. In addition, if the resistance value of resistance element 92 is indicated by R, then Ic=dV/R. Here, if the temperature dependency of R is negligible, Ic is proportional to absolute temperature T. Thus, the temperature characteristic of Ic is positive.
This Ic, being less likely to be affected by variations of an external power-supply potential extVdd or by process variations, is used in various internal circuits 82 to 85 within the semiconductor integrated circuit device. A gate potential of P-channel MOS transistors 94 and 95 is provided as a bias potential VBH to gates of P-channel MOS transistors of internal circuits 82 and 83, and a constant current Ic flows through internal circuits 82 and 83. Moreover, a gate potential of N-channel MOS transistors 96 and 97 is provided as a bias potential VBL to gates of N-channel MOS transistors of internal circuits 84 and 85, and constant current Ic flows through internal circuits 84 and 85.
A reference potential generating circuit 100 as shown in FIG. 15, for example, is provided to an internal circuit 83. Reference potential generating circuit 100 includes P-channel MOS transistors 101 to 104 connected in series between an external power-supply potential extVdd line and a ground potential GND line. P-channel MOS transistor 101 is equal in size to P-channel MOS transistor 94. The gate of P-channel MOS transistor 101 receives bias potential VBH generated by constant-current source circuit 81. Gates of P-channel MOS transistors 102 and 103 are both connected to the drain of P-channel MOS transistor 103. The gate of P-channel MOS transistor 104 is grounded. The drain of P-channel MOS transistor 101 becomes an output node N101.
P-channel MOS transistors 102 and 103 each operate as a resistance element. P-channel MOS transistor 104 is large enough for Ic and operates as a diode. P-channel MOS transistor 101 and P-channel MOS transistor 94 of constant-current source circuit 81 form a current mirror circuit so that constant current Ic flows through P-channel MOS transistors 101 to 104 of reference potential generating circuit 100. If the total resistance value of P-channel MOS transistors 102 and 103 is R102, and the threshold voltage of P-channel MOS transistor 104 is Vt104, a reference potential VR=Icxc3x97R102+Vt104 would be output from output node N101.
Here, Icxc3x97R102 takes on the positive temperature characteristic of Ic, while the temperature characteristic of Vt104 is negative. By setting the positive temperature characteristic of Icxc3x97R102 and the negative temperature characteristic of Vt104 to balance out, the temperature characteristic of reference potential VR can be cancelled. Otherwise, either one of resistance value component Icxc3x97R102 and threshold component Vt104 can be made dominant so that reference potential VR indicates either the positive or the negative temperature characteristic.
Reference potential VR is used as a reference when generating various internal potentials, such as an internal power-supply potential intVdd that is lower than an external power-supply potential extVdd, and a boosted potential Vpp for transmitting the exact high data level by keeping the resistance value of an N-channel MOS transistor in its conductive state sufficiently small.
Internal circuit 84 is provided with a Vbb level detection circuit 110 as the one shown in FIG. 16, for example. Vbb level detection circuit 110 includes P-channel MOS transistors 111, 112, N-channel MOS transistors 113 to 117, fuses 118 to 120, and a comparator 121. MOS transistors 111, 113 to 116 are connected in series between an external power-supply potential extVdd line and a substrate potential Vbb line. MOS transistors 112, 117 are connected in series between an external power-supply potential extVdd line and a ground potential GND line.
Gates of P-channel MOS transistors 111, 112 are both connected to the drain (node N111) of P-channel MOS transistor 111. P-channel MOS transistors 111 and 112 form a current mirror circuit. Gates of N-channel MOS transistors 113, 117 receive bias potential VBL generated in constant-current source circuit 81. Gates of N-channel MOS transistors 114 to 116 are all grounded. Fuses 118 to 120 are connected in parallel to N-channel MOS transistors 114 to 116, respectively.
Comparator 121 compares the potential of node N111 with the potential of a node N112 to output a charge pump activating signal xcfx86C. When the potential of node N111 is higher than the potential of node N112, signal xcfx86C attains the active level, or the logic high or xe2x80x9cHxe2x80x9d level, whereas when the potential of node N111 is lower than the potential of node N112, signal xcfx86C attains the inactive level, or the logic low or xe2x80x9cLxe2x80x9d level.
N-channel MOS transistors 114 to 116 each operate as a resistance element. If the resistance value between a node N113 and a substrate potential Vbb line is Rb, the potential of the source (node N113) of N-channel MOS transistor 113 attains ground potential GND when Vbb=Rbxc3x97Ic, whereby the potentials of node N111 and node N112 become equal. Resistance value Rb can be regulated by blowing or not blowing fuses 118 to 120.
When substrate potential Vbb is higher than the set value (xe2x88x92Rbxc3x97Ic), the potential of node N113 becomes higher than ground potential GND, and the current that flows through N-channel MOS transistor 113 becomes smaller than constant current Ic. Currents of the same value flow through MOS transistors 111 to 113, respectively, while N-channel MOS transistor 117 can conduct a current Ic greater than the current that flows through each one of MOS transistors 111 to 113. Thus, the potential of node N111 becomes higher than the potential of node N112, and charge pump activating signal xcfx86C attains the active level, or the xe2x80x9cHxe2x80x9d level. Accordingly, a charge pump circuit 122 ejects positive charges from the substrate (or feeds negative charges into the substrate), reducing substrate potential Vbb.
When substrate potential Vbb is lower than the set value (xe2x88x92Rbxc3x97Ic), the potential of node N113 becomes lower than a ground potential GND, and the current that flows through N-channel MOS transistor 113 becomes greater than constant current Ic. Currents of the same value flow through MOS transistors 111 to 113, respectively, and current Ic that can flow through N-channel MOS transistor 117 is smaller than the current that flows through each of MOS transistors 111 to 113. Thus, the potential of node N112 becomes higher than the potential of node N111, and charge pump activating signal xcfx86C attains the inactive level, or the xe2x80x9cLxe2x80x9d level, whereby the charge pump circuit 122 is rendered inactive. Accordingly, substrate potential Vbb is held at the set value (xe2x88x92Rbxc3x97Ic). Further, while substrate potential Vbb is proportional to absolute temperature T when employing a Vbb level detection circuit 110 of FIG. 16, the temperature characteristic of substrate potential Vbb can be controlled by connecting a diode in series with N-channel MOS transistors 114 to 116, as described in relation to reference potential generating circuit 100 of FIG. 15.
Moreover, internal circuit 82 is provided with a ring oscillator 130 as the one shown in FIG. 17, for example. Ring oscillator 130 includes N stages (N is an odd number) of inverters 131.1 to 131.N connected in a ring-like manner, and P-channel MOS transistors 134.1 to 134.N each connected between an external power-supply potential extVdd line and the respective power-supply node of inverters 131.1 to 131.N. Each of inverters 131.1 to 131.N includes a P-channel MOS transistor 132 and an N-channel MOS transistor 133 connected in series between a power-supply node and a ground potential GND line.
The drivability of each of inverters 131.1 to 131.N is determined by current Ic that can flow through P-channel MOS transistors 134.1 to 134.N. Since current Ic is not dependent on variations of an external power-supply potential extVdd or on process variations, ring oscillator 130 provides oscillation at a stable frequency.
In addition, the temperature characteristic of the frequency of an output clock signal CLK of ring oscillator 130, like the constant current, is positive. Thus, ring oscillator 130 is advantageously used as a ring oscillator for determining the frequency of a self-refresh operation in a DRAM.
Since, in general, the period for which DRAM holds data is shorter when the temperature is higher, it is desirable that the refresh frequency becomes higher as the temperature becomes higher. With a ring oscillator having a plurality of inverters merely connected in the shape of a ring, however, the oscillation frequency becomes lower as the temperature increases. Consequently, if the frequency was set at a high temperature, the frequency becomes extremely high at a low temperature, and the refresh operation is performed more often than necessary, requiring a greater dissipation current. On the other hand, with ring oscillator 130 shown in FIG. 17, the temperature characteristic of the oscillation frequency is positive so that it matches the temperature characteristic of the DRAM""s period for holding data.
In addition, bias potentials VBH and VBL are utilized to limit the through current of a circuit to a small value by taking advantage of the small constant current Ic.
Since the constant current Ic generated in constant-current source circuit 81 is generally of a very small value (for instance, on the order of 1 xcexcA) and since the circuit forms a closed loop, noise countermeasures are requisite. The use of a low pass filter described in relation to FIG. 15 also is one of the noise countermeasures. Moreover, such countermeasures are taken as shortening the lengths of the lines of bias potentials VBH and VBL between constant-current source circuit 81 and internal circuits 82 to 85 as well as shielding of these lines.
These countermeasures, however, are not always sufficient. Let us consider, for instance, the operation of Vbb level detection circuit 110 of FIG. 16 upon power-on. While the power is off, substrate potential Vbb is substantially at a ground potential GND. When power is provided, constant-current source circuit 81 starts to operate before any of the other circuits. This is due to the fact that, since constant current Ic is utilized in a number of circuits, in order for these circuits to perform a normal operation, it is necessary for the operation of constant-current source circuit 81 quickly to settle to its steady state. Then, Vbb level detection circuit 110 decides that substrate potential Vbb is high, and causes the charge pump circuit to operate. Since the load capacitance of substrate potential Vbb is extremely large and substrate potential Vbb is required to have attained a normal level approximately 200 xcexcs after the power-on, the charge pump circuit is set to have a great charge-supplying ability. Thus, substrate potential Vbb is pulled down at a significant speed.
At this time, bias potential VBL line and substrate potential Vbb line are coupled by the parasitic capacitance of N-channel MOS transistor 113 (capacitance resulting between substrates or resulting from the source and the drain overlapping the gate), and the VBL line is pulled toward the direction of ground potential GND. As a result, constant-current source circuit 81 may no longer be able to conduct the current, and a significantly long time may be required before the entire semiconductor integrated circuit device starts to operate stably.
Moreover, when ring oscillator 130 of FIG. 17 is not driven steadily but is driven only upon receiving some kind of activating signal, the dissipation current in ring oscillator 130 greatly varies in time, and noise is introduced to bias potential VBH.
The main object of the present invention is to provide a semiconductor device that prevents the noise generated in an internal circuit from adversely affecting a constant-current source circuit and that allows a stable operation of the internal circuit itself.
To put it simply, according to the present invention, a buffer circuit is provided between a constant-current source circuit and an internal circuit, for receiving at an input node an output potential of the constant-current source circuit to control the potential of an output node such that the potential of the output node is the same as that of the input node. Thus, the noise generated in an internal circuit is dampened by the buffer circuit so that the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit and the stable operation of the internal circuit itself is achieved.
Preferably, a setting circuit is further provided for selectively setting a path to provide a bias potential that is output from the constant-current source circuit to an internal circuit via the buffer circuit or a path to provide the bias potential directly to the internal circuit without the intervention of the buffer circuit. In this case, the buffer circuit is used only when required so that no unnecessary current is dissipated wastefully.
Preferably, the setting circuit includes a first fuse connected between an input node and an output node of the buffer circuit and a second fuse for activating the buffer circuit when blown. In this case, the setting circuit is easily configured.
Preferably, a control circuit is further provided that sets the drivability of the buffer circuit, which can be switched between at least two levels of high and low, at a high level during the noise generation period or the period during which noise is generated in an internal circuit, and at a low level during other times. In this case, the dampening of the generated noise is ensured, and the dissipation current can be reduced.
Preferably, the noise generation period of an internal circuit is the period from the time when an external power-supply potential is provided to the semiconductor device up to the time when an internal power-supply potential attains a predetermined potential level. In this case, the constant-current source circuit and the like are prevented from being adversely affected by the noise generated at power-on.
Preferably, the semiconductor device is formed on a semiconductor substrate and is further provided with a potential detection circuit for detecting whether or not the potential of the semiconductor substrate exceeds a predetermined target potential and for outputting an activating signal when the potential of the semiconductor substrate has not exceeded a predetermined target potential, and a charge pump circuit for supplying charges to the semiconductor substrate corresponding to the outputting of the activating signal from the potential detection circuit. The noise generation period of an internal circuit is the period during which the activating signal is being output from the potential detection circuit. In this case, the constant-current source circuit and the like are prevented from being adversely affected by the noise generated while the charge pump circuit is driven.
Preferably, a first capacitor and a second capacitor are further provided, connected between an input node or an output node of a buffer circuit and a reference potential line, respectively. In this case, the rapid change in the potentials of the input node and the output node of the buffer circuit can be prevented so that input and output of the buffer circuit can be stabilized.
Preferably, the buffer circuit includes a first transistor having an input electrode connected to an input node, a second transistor having an input electrode and a first electrode connected to an output node, a current mirror circuit for providing to an output node a current having the same value as the current that flows through the first transistor, and a resistance element for limiting a sum of the currents flowing through the first and second transistors to a prescribed value. In this case, the buffer circuit is easily configured.
Preferably, a plurality of internal circuits are provided, and the plurality of internal circuits are divided into a plurality of groups according to the noise generation period and the types of the noise generated. The buffer circuit is provided corresponding to each of these groups, and transmits an output potential of a constant-current source circuit to each internal circuit belonging to a corresponding group. In this case, the noise generated in a group of internal circuits can be prevented from adversely affecting the internal circuits of another group.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.